1. Field of the Invention
The present invention relates to a semiconductor memory device, and specifically to a memory array for reading information in memory cells using bit lines and virtual GND lines.
2. Description of the Related Art
There is a conventional system for reading information in memory cells of an MROM (Mask Read Only Memory) using bit lines and virtual GND lines.
FIG. 6 is a conceptual view illustrating a configuration of a memory array 600 in a conventional MROM operating in such a system.
A memory array 600 shown in FIG. 6 includes a plurality of bit lines 601 and a plurality of virtual GND lines 602. A MOSFET 603 or a MOSFET 603A is connected between each pair of adjacent bit line 601 and virtual GND line 602. The MOSFETs 603 and 603A store binary information in the memory array 600 as described later and will be referred to as "memory cell transistors", hereinafter. In FIG. 6, the memory cell transistor 603 is a selected memory cell transistor, from which information is to be read. A word line 605 is provided perpendicular to the bit lines 601 and the virtual GND lines 602. The word line 605 is connected to a gate electrode 604 of each of the memory cell transistors 603 and 603A. A plurality of memory cell transistors 603 and 603A are connected to one word line 605, thus improving the space efficiency of the memory cell. The bit line 601 connected to the selected memory cell transistor 603 is connected to a charging circuit 1 and a sensing circuit 2, and the virtual GND line 602 connected to the selected memory cell transistor 603 is grounded. The charging circuit 1 is one exemplary device for charging the bit line 601.
The memory array 600 is produced so as to include the following two types of memory cell transistors. One type of memory cell transistors have a relatively high threshold level; i.e., are not turned ON when a certain voltage is applied by the word line 605 through the gate electrode 604 (OFF transistors). The other type of memory cell transistors have a relatively low threshold level; i.e., are turned ON when a certain voltage is applied by the word line 605 through the gate electrode 604 (ON transistors). Thus, binary information is stored in the memory array 600.
In the conventional memory array 600, the information is read in the following manner. The bit line 601 connected to the memory cell transistor 603 is charged by the charging circuit 1, and the virtual GND line 602 connected to the memory cell transistor 603 is grounded. In this potential state, the difference between the ON transistors and the OFF transistors is read by the sensing circuit 2. Thus, the information stored in the memory cell transistor 603 is determined to be ON or OFF.
One generally known system for reading information in such a memory array at a high speed is a hierarchical bit line system. A memory array operating in this system includes a main bit line, a sub bit line, and a bank transistor for connecting the main bit line and the sub bit line.
The main bit line mainly is formed of a metal layer, and a sub bit line mainly is formed of a diffusion layer. The diffusive layer acts as a source and a drain of each memory cell transistor. A group of memory cells respectively having gate electrodes connected to word lines WL1 through WLn in a bank transistor is referred to as a bank. In order to improve the space efficiency of the memory cell, one main bit line is connected to a plurality of sub bit lines through the bank transistor on a bank-by-bank basis. High speed reading is realized by accessing the memory cell through the main bit line on a bank-by-bank basis.
FIG. 7 is a configuration of a memory array circuit 700 of the hierarchical bit line system.
As shown in FIG. 7, the memory array circuit 700 includes a memory array 40, which includes a plurality of memory cell transistors arranged in an array. In more detail, the memory array 40 includes a plurality of word lines (e.g., word lines WL0 through WLn). Each word line (e.g., word line WL0) is connected to a gate of each memory cell transistor of a plurality of memory cell transistors (e.g., memory cell transistors M0 through M14). A plurality of bit lines and a plurality of virtual GND lines are provided perpendicular to the word lines. In FIG. 7, the main bit lines are indicated by MB0, MB2, MB4, MB6 and MB8; and the virtual GND lines are indicated by MB1, MB3, MB5 and MB7. Drains of the memory cell transistors connected to one word line are respectively connected to sources of the adjacent memory cell transistors. Accordingly, the memory cell transistors are connected in series. The sub bit lines are connected between a source of each memory cell transistor and a drain of an adjacent memory cell transistor.
The main bit line MB2 and the virtual GND line MB3 will be described, hereinafter. The main bit line MB2 is connected to sub bit lines SB2 and SB4. The sub bit line SB2 is connected to a drain of a memory cell transistor M1 and a source of the memory cell transistor M2 through a bank transistor BK1-2. The sub bit line SB4 is connected to a drain of a memory cell transistor M3 and a source of the memory cell transistor M4 through a bank transistor BK1-1. Since a gate of the bank transistor BK1-1 is connected to a bank selection line BKL2, the bank transistor BK1-1 is selected by the bank selection line BKL1. Since a gate of the bank transistor BK1-2 is connected to a bank selection line BKL2, the bank transistor BK1-2 is selected by the bank selection line BKL2. A drain of the memory cell transistor M2 and a source of the memory cell transistor N3 are connected to a sub bit line SB3.
The main bit line MB2 is connected to, for example, a block selection circuit 30, a charging and GND selection circuit 10 and a charging and sensing circuit 20. In more detail, a current from the main bit line MB2 is input to the charging and GND selection circuit 10 through a transistor TR1 of the block selection circuit 30. The current is then divided into two so as to be sent separately through transistors TR2 and TR3. The divided currents are input to the charging circuit 1 in the charging and sensing circuit 20. The current sent through the transistor TR3 in the charging and GND selection circuit 10 is detected by a sensing circuit 50 in the charging and sensing circuit 20. Gates of the transistors TR1, TR2 and TR3 are respectively connected to lines BLOCKSEL1, BSEL1 and BSEL2 and thus controlled.
A drain of the memory cell transistor M4 and a source of a memory cell transistor M5 are connected to a sub bit line SB5. The sub bit line SB5 is connected to a virtual GND line MB3 through a bank transistor BK3-2. A gate of the bank transistor BK3-2 is connected to a bank selection line BKL3. A current from the virtual GND line MB3 is input to the charging and GND selection circuit 10 through a transistor TR4 of the block selection circuit 30. The current is then divided into two so as to be sent separately through transistors TR5 and TR6. The current sent through the transistor TR5 is grounded in the charging and GND selection circuit 10. The current sent through the transistor TR6 is input to the charging circuit 1 in the charging and sensing circuit 20. Gates of the transistors TR4, TR5 and TR6 are respectively connected to lines BLOCKSEL1, VGSEL1 and VGSEL2 and thus controlled.
The configuration regarding the other main bit lines and virtual GND lines are substantially the same as the configuration regarding the main bit line MB2 and the virtual GND line MB3, and thus will not be described herein.
The charging and GND selection circuit 10 and the charging and sensing circuit 20 can be connected to a plurality of block selection circuits 30.
The memory array circuit 700 operates in the following manner for reading information from the memory cell transistor M4 (i.e., when the memory cell transistor M4 is selected).
The word line WL0 connected to the gate of the memory cell transistor M4 becomes HIGH (high level) and the other word lines WL1 through WLn become LOW (low level). In order to cause the bank transistors BK1-1 to be an ON transistor, the bank selection line BKL1 becomes HIGH. In order to cause the bank transistors BK3-2 to be an ON transistor, the bank selection line BKL3 becomes HIGH. The bank selection lines BKL2 and BKL4 become LOW.
Then, current paths of (MB2)-(BK1-1)-(SB4) and (SB5)-(BK3-2)-(MB3) are formed. In the case where the memory cell transistor M4 is an ON transistor, when the lines BSEL2, VGSEL1, BLOCKSEL1 become HIGH and the lines BSEL1 and VGSEL2 become LOW, the selected main bit line MB2 is made to be at the charging level and the selected virtual GND line MB3 is made to be at the GND level. Thus, the current flows in the path of (MB2)-(BK1-1)-(SB4)-(M4)-(SB5)-(BK3-2)-(MB3).
The sensing circuit 50 connected to the selected main bit line MB2 through the transistor TR1 determines that the memory cell transistor M4 is an ON transistor based on, for example, a change in the level of the selected main bit line MB2 from the charging level.
However, in the case where the selected memory cell transistor M4 is an OFF transistor and the non-selected memory cell transistors M3, M2, M1, M0 and the like in the vicinity of the memory cell transistor M4 are ON transistors, a current path of (M4)-(M3)-(M2)-(M1) . . . is formed although the memory cell transistor M4 is an OFF transistor. The reason is that the gates of the memory cell transistors M4, M3, M2, M1 and M0 are connected to the same word line WL0.
Accordingly, when the selected main bit line MB2 is made to be at the charging level, the current flows in the path of (MB2)-(BK1-1)-(SB4)-(M3)-(M2)-(M1) . . . . The current flowing in this path is referred to as a "bypass current" I1" (not shown). As a result, the selected memory cell transistor M4 behaves as an ON transistor though being an OFF transistor. In order to prevent such a behavior, the non-selected bit lines and the non-selected virtual GND lines are made to be at the charging level in the conventional circuit.
In the memory array circuit 700 shown in FIG. 7, the non-selected bit line MB0 and the non-selected virtual GND line MB1 are made to be at the charging level. As a result, the sub bit lines SB0 and SB1 are made to be at the charging level through respective bank transistors. In such a manner, even when the memory cell transistors M3, M2, M1, M0 and the like are ON transistors, the bypass current I1 is not generated. Therefore, the selected main bit line MB2 connected to the memory cell transistor M4 behaves differently when the memory cell transistor M4 is an OFF transistor from when the memory cell transistor M4 is an ON transistor. Thus, the information from the selected memory cell transistor M4 is read in a stable manner.
However, the above-mentioned system for preventing the bypass current I1 undesirably reduces the reading margin when the selected transistor is an ON transistor. In order to solve the problem, Japanese Laid-Open Publication No. 10-11991 proposes a specific system for connecting memory cell transistors and the bank transistors, as described below with reference to FIG. 9.
With reference to FIG. 7, the bypass current I1 will be described in more detail.
As described above, for reading information from the memory cell transistor M4, the selected main bit line MB2 is made to be at the charging level and the selected virtual GND line MB3 is made to be at the GND level. Also as described above, the non-selected main bit line MB0 and the non-selected virtual GND line MB1 are made to be at the charging level. The non-selected main bit line MB4 and the non-selected virtual GND line MB5 are also charged for the following reason.
In general, one cycle of reading operation reads information from a plurality of memory cell transistors simultaneously. In the memory array circuit 700, information in the memory cell transistor M12 is readable simultaneously with the information in the memory cell transistor M4. The non-selected main bit line MB4 and the non-selected virtual GND line MB5 are charged in order to prevent generation of a bypass current, which would otherwise be generated and flow from the sub bit line SB12 when information is read from the memory cell transistor M12.
Accordingly, when the memory cell transistors M5, M6, M7, M8 and the like in the vicinity of the memory cell transistor M4 are ON transistors, the non-selected bit line MB4 and the non-selected virtual GND line MB5 are made to be at the charging level. As a result, the sub bit lines SB4 and SB5 are made to be at the charging level through the respective bank transistors. Thus, a current path of (SB8)-(M7)-(M6)-(M5)-(M4)-(SB4) is formed. A current flowing in this path is referred to as a "bypass current I2". When the selected memory cell transistor M4 is an ON transistor, the bypass current I2 reduces the reading current flowing in the path of (MB2)-(BK1-1)-(SB4)-(M4)-(SB5)-(BK3-2)-(MB3). Such a reduction in the reading current decreases the reading speed of the information from the memory cell transistors and can undesirably cause a reading error of the information.
FIG. 8 shows a configuration of the memory array 40 including a plurality of memory cell transistors connected to one word line. When the non-selected bit line MB4 and non-selected virtual GND line MB5 are charged, the bypass current I2 is generated, which reduces the reading current for reading information from the memory cell transistor M4 when the memory cell transistor M4 is an ON transistor. However, the non-selected main bit line MB4 and the non-selected GND line MB5 indispensably need to be charged for reading information from the memory cell transistor M12 when the memory cell transistor M12 is an OFF transistor.
According to another possible solution for the problem of the bypass current, the number of the non-selected memory cell transistors between the memory cell transistors M4 and M12 is increased, and non-selected main bit lines 801 and non-selected virtual GND lines 802 are charged only to a minimum required level. In this manner, a current corresponding to the bypass current I2 flowing into the selected main bit line is reduced. However, this system does not fundamentally eliminate the current corresponding to the bypass current I2.
In the case where all the non-selected memory cell transistors between the memory cell transistors M4 and M12 are ON transistors, the charging of the non-selected main bit line MB4 and the non-selected GND line MB5, which is indispensable for reading the information from the memory cell transistor M12 when the memory cell transistor M12 is an OFF transistor, merely reduces the current corresponding to the bypass current I1 and does not fundamentally solve the problem of reducing the current for reading information from the memory cell transistor M4 when the memory cell transistor M4 is an ON transistor. The current corresponding to this bypass current I2 will be referred to as a "reading parasitic current", hereinafter.
A semiconductor memory device described in Japanese Laid-Open Publication No. 10-11991 will be described with reference to FIG. 9. FIG. 9 is a circuit configuration of a semiconductor memory device 300.
In the semiconductor memory device 300, bank transistors connected to the main bit lines BS0 through BS3 and bank transistors connected to the main bit lines BS4 through BS7 are connected to bank selection lines BKL1 through BKL4 in different manners. When the memory cell transistor M4 is selected, the main bit line BS4 and the virtual GND line BS3 are selected. Since the non-selected main bit line BS1 is at the charging level at this point, the current flows to the selected virtual GND line BS3 through the non-selected memory cell transistors M2 and M3. However, since there are only two non-selected memory cell transistors M2 and M3 through which the current flows to the selected virtual GND line BS3, the reading parasitic current can be reduced.
The semiconductor memory device 300 does not solve the problem that the reading parasitic current is generated although reducing the amount thereof.